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quad-channel digital isolators data sheet adum2400 / adum2401 / adum2402 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2011 analog devices, inc. all rights reserved. features low power operation 5 v operation 1.0 ma per channel maximum @ 0 mbps to 2 mbps 3.5 ma per channel maximum @ 10 mbps 31 ma per channel maximum @ 90 mbps 3 v operation 0.7 ma per channel maximum @ 0 mbps to 2 mbps 2.1 ma per channel maximum @ 10 mbps 20 ma per channel maximum @ 90 mbps bidirectional communication 3 v/5 v level translation high temperature operation: 105c high data rate: dc to 90 mbps (nrz) precise timing characteristics 2 ns maximum pulse width distortion 2 ns maximum channel-to-channel matching high common-mode transient immunity: >25 kv/s output enable function 16-lead soic wide body package version (rw-16) 16-lead soic wide body enhanced creepage version (ri-16) safety and regulatory approvals (ri-16 package) ul recognition: 5000 v rms for 1 minute per ul 1577 csa component acceptance notice #5a iec 60601-1: 250 v rms (reinforced) iec 60950-1: 400 v rms (reinforced) vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 846 v peak applications general-purpose, high voltage, multichannel isolation medical equipment motor drives power supplies general description the adum240x 1 are 4-channel digital isolators based on analog devices, inc., i coupler? technology. combining high speed cmos and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics that are superior to alternatives, such as optocoupler devices. by avoiding the use of leds and photodiodes, i coupler devices remove the design difficulties commonly associated with opto- couplers. the typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple 1 protected by u.s. patents 5,952,849; 6,873,065; and 7,075,329. functional block diagrams encode decode encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic v id nc gnd 1 v dd2 gnd 2 v oa v ob v oc v od v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05007-001 adum2400 figure 1. adum2400 decode encode encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic v od v e1 gnd 1 v dd2 gnd 2 v oa v ob v oc v id v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05007-002 adum2401 figure 2. adum2401 decode encode decode encode encode decode encode decode v dd1 gnd 1 v ia v ib v oc v od v e1 gnd 1 v dd2 gnd 2 v oa v ob v ic v id v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05007-003 adum2402 figure 3. adum2402 i coupler digital interfaces and stable performance characteristics. furthermore, i coupler devices run at one-tenth to one-sixth the power of optocouplers at comparable signal data rates. the adum240x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the ordering guide). the adum240x models operate with the supply voltage of either side ranging from 2.7 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. in addition, the adum240x provide low pulse width distortion (<2 ns for crwz grade) and tight channel-to-channel matching (<2 ns for crwz grade). the adum240x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions
adum2400/adum2401/adum2402 data sheet rev. d | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics5 v operation................................ 3 ? electrical characteristics3 v operation................................ 5 ? electrical characteristicsmixed 5 v/3 v or 3 v/5 v operation ....................................................................................... 7 ? package characteristics ............................................................. 10 ? regulatory information ............................................................. 10 ? insulation and safety-related specifications .......................... 10 ? din v vde v 0884-10 (vde v 0884-10) insulation characteristics ............................................................................ 11 ? recommended operating conditions .................................... 11 ? absolute maximum ratings ......................................................... 12 ? esd caution................................................................................ 12 ? pin configurations and function descriptions ......................... 13 ? typical performance characteristics ........................................... 16 ? application information ................................................................ 18 ? pc board layout ........................................................................ 18 ? propagation delay-related parameters ................................... 18 ? dc correctness and magnetic field immunity .......................... 18 ? power consumption .................................................................. 19 ? insulation lifetime ..................................................................... 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 22 ? revision history 8/11rev. c to rev d added 16-lead soic_ic .................................................. universal changes to features section and general description section ................................................................................................ 1 changes to table 5 and table 6 ..................................................... 10 changes to table 8 endnote .......................................................... 11 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21 7/08rev. b to rev. c changes to layout ............................................................................ 1 changes to table 6 .......................................................................... 10 6/07rev. a to rev. b updated vde certification throughout ...................................... 1 changes to features and note 1 ..................................................... 1 changes to figure 1, figure 2, and figure 3.................................. 1 changes to regulatory information ............................................ 10 changes to table 7 .......................................................................... 11 changes to insulation lifetime section ....................................... 20 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21 1/06rev. 0 to rev. a changes to regulatory information section ............................... 13 updated outline dimensions ....................................................... 23 changes to ordering guide .......................................................... 23 9/05revision 0: initial version
data sheet adum2400/adum2401/adum2402 rev. d | page 3 of 24 specifications electrical characteristics5 v operation 1 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v. all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. table 1. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.50 0.53 ma output supply current pe r channel, quiescent i ddo (q) 0.19 0.21 ma adum2400 total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 2.2 2.8 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 0.9 1.4 ma dc to 1 mhz logic signal frequency 10 mbps (brwz and crwz grades only) v dd1 supply current i dd1 (10) 8.6 10.6 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 2.6 3.5 ma 5 mhz logic signal frequency 90 mbps (crwz grade only) v dd1 supply current i dd1 (90) 70 100 ma 45 mhz logic signal frequency v dd2 supply current i dd2 (90) 18 25 ma 45 mhz logic signal frequency adum2401 total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 1.8 2.4 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 1.2 1.8 ma dc to 1 mhz logic signal frequency 10 mbps (brwz and crwz grades only) v dd1 supply current i dd1 (10) 7.1 9.0 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 4.1 5.0 ma 5 mhz logic signal frequency 90 mbps (crwz grade only) v dd1 supply current i dd1 (90) 57 82 ma 45 mhz logic signal frequency v dd2 supply current i dd2 (90) 31 43 ma 45 mhz logic signal frequency adum2402 total supply current, four channels 2 dc to 2 mbps v dd1 or v dd2 supply current i dd1 (q) , i dd2 (q) 1.5 2.1 ma dc to 1 mhz logic signal frequency 10 mbps (brwz and crwz grades only) v dd1 or v dd2 supply current i dd1 (10) , i dd2 (10) 5.6 7.0 ma 5 mhz logic signal frequency 90 mbps (crwz grade only) v dd1 or v dd2 supply current i dd1 (90) , i dd2 (90) 44 62 ma 45 mhz logic signal frequency for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 2.0 v logic low input threshold v il , v el 0.8 v logic high output voltages v oah , v obh , v och , v odh (v dd1 or v dd2 ) ? 0.1 5.0 v i ox = ?20 a, v ix = v ixh (v dd1 or v dd2 ) ? 0.4 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum240xarwz minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 50 65 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/ t pskod 50 ns c l = 15 pf, cmos signal levels
adum2400/adum2401/adum2402 data sheet rev. d | page 4 of 24 parameter symbol min typ max unit test conditions adum240xbrwz minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 32 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 15 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 6 ns c l = 15 pf, cmos signal levels adum240xcrwz minimum pulse width 3 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 4 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 18 27 32 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 10 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 2 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input dynamic supply current per channel 9 i ddi (d) 0.19 ma/mbps output dynamic supply current per channel 9 i ddo (d) 0.05 ma/mbps 1 all voltages are relative to their respective ground. 2 supply current values are for all four ch annels combined running at identical data rates. output supply current values are spe cified with no output load present. the supply current associated with an individual ch annel operating at a given data rate can be calculated as de scribed in the power consumption section. see figure 8 through figure 10 for information on per ch annel supply current as a function of data rate for unloaded an d loaded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for adum2400/adum2401/ adum2402 channel configurations. 3 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposing di rectional channel-to-channel match ing is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 8 through figure 10 for information on per channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating per channel supply current for a given data rate.
data sheet adum2400/adum2401/adum2402 rev. d | page 5 of 24 electrical characteristics3 v operation 1 2.7 v v dd1 3.6 v, 2.7 v v dd2 3.6 v. all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.0 v. table 2. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.26 0.31 ma output supply current pe r channel, quiescent i ddo (q) 0.11 0.14 ma adum2400 total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 1.2 1.9 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 0.5 0.9 ma dc to 1 mhz logic signal frequency 10 mbps (brwz and crwz grades only) v dd1 supply current i dd1 (10) 4.5 6.5 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 1.4 2.0 ma 5 mhz logic signal frequency 90 mbps (crwz grade only) v dd1 supply current i dd1 (90) 37 65 ma 45 mhz logic signal frequency v dd2 supply current i dd2 (90) 11 15 ma 45 mhz logic signal frequency adum2401 total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 1.0 1.6 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 0.7 1.2 ma dc to 1 mhz logic signal frequency 10 mbps (brwz and crwz grades only) v dd1 supply current i dd1 (10) 3.7 5.4 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 2.2 3.0 ma 5 mhz logic signal frequency 90 mbps (crwz grade only) v dd1 supply current i dd1 (90) 30 52 ma 45 mhz logic signal frequency v dd2 supply current i dd2 (90) 18 27 ma 45 mhz logic signal frequency adum2402 total supply current, four channels 2 dc to 2 mbps v dd1 or v dd2 supply current i dd1 (q) , i dd2 (q) 0.9 1.5 ma dc to 1 mhz logic signal frequency 10 mbps (brwz and crwz grades only) v dd1 or v dd2 supply current i dd1 (10) , i dd2 (10) 3.0 4.2 ma 5 mhz logic signal frequency 90 mbps (crwz grade only) v dd1 or v dd2 supply current i dd1 (90) , i dd2 (90) 24 39 ma 45 mhz logic signal frequency for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 1.6 v logic low input threshold v il , v el 0.4 v logic high output voltages v oah , v obh , v och , v odh (v dd1 or v dd2 ) ? 0.1 3.0 v i ox = ?20 a, v ix = v ixh (v dd1 or v dd2 ) ? 0.4 2.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum240xarwz minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 50 75 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/ t pskod 50 ns c l = 15 pf, cmos signal levels
adum2400/adum2401/adum2402 data sheet rev. d | page 6 of 24 parameter symbol min typ max unit test conditions adum240xbrwz minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 38 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 22 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 6 ns c l = 15 pf, cmos signal levels adum240xcrwz minimum pulse width 3 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 4 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 34 45 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 16 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 2 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 3 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input dynamic supply current per channel 9 i ddi (d) 0.10 ma/mbps output dynamic supply current per channel 9 i ddo (d) 0.03 ma/mbps 1 all voltages are relative to their respective ground. 2 supply current values are for all four ch annels combined running at identical data rates. output supply current values are spe cified with no output load present. the supply current associated with an individual ch annel operating at a given data rate can be calculated as de scribed in the power consumption section. see figure 8 through figure 10 for information on per ch annel supply current as a function of data rate for unloaded an d loaded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for adum2400/adum2401/ adum2402 channel configurations. 3 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposing di rectional channel-to-channel match ing is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 8 through figure 10 for information on per channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating per channel supply current for a given data rate.
data sheet adum2400/adum2401/adum2402 rev. d | page 7 of 24 electrical characteristicsmixed 5 v/3 v or 3 v/5 v operation 1 5 v/3 v operation: 4.5 v v dd1 5.5 v, 2.7 v v dd2 3.6 v. 3 v/5 v operation: 2.7 v v dd1 3.6 v, 4.5 v v dd2 5.5 v. all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. all typical specifica tions are at t a = 25c; v dd1 = 3.0 v, v dd2 = 5 v; or v dd1 = 5 v, v dd2 = 3.0 v. table 3. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 5 v/3 v operation 0.50 0.53 ma 3 v/5 v operation 0.26 0.31 ma output supply current per channel, quiescent i ddo (q) 5 v/3 v operation 0.11 0.14 ma 3 v/5 v operation 0.19 0.21 ma adum2400 total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.2 2.8 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 1.2 1.9 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 5 v/3 v operation 0.5 0.9 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 0.9 1.4 ma dc to 1 mhz logic signal frequency 10 mbps (brwz and crwz grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 8.6 10.6 ma 5 mhz logic signal frequency 3 v/5 v operation 4.5 6.5 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 5 v/3 v operation 1.4 2.0 ma 5 mhz logic signal frequency 3 v/5 v operation 2.6 3.5 ma 5 mhz logic signal frequency 90 mbps (crwz grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 70 100 ma 45 mhz logic signal frequency 3 v/5 v operation 37 65 ma 45 mhz logic signal frequency v dd2 supply current i dd2 (90) 5 v/3 v operation 11 15 ma 45 mhz logic signal frequency 3 v/5 v operation 18 25 ma 45 mhz logic signal frequency adum2401 total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 1.8 2.4 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 1.0 1.6 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 5 v/3 v operation 0.7 1.2 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 1.2 1.8 ma dc to 1 mhz logic signal frequency 10 mbps (brwz and crwz grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 7.1 9.0 ma 5 mhz logic signal frequency 3 v/5 v operation 3.7 5.4 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 5 v/3 v operation 2.2 3.0 ma 5 mhz logic signal frequency 3 v/5 v operation 4.1 5.0 ma 5 mhz logic signal frequency 90 mbps (crwz grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 57 82 ma 45 mhz logic signal frequency 3 v/5 v operation 30 52 ma 45 mhz logic signal frequency
adum2400/adum2401/adum2402 data sheet rev. d | page 8 of 24 parameter symbol min typ max unit test conditions v dd2 supply current i dd2 (90) 5 v/3 v operation 18 27 ma 45 mhz logic signal frequency 3 v/5 v operation 31 43 ma 45 mhz logic signal frequency adum2402 total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 1.5 2.1 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 0.9 1.5 ma dc to 1 mhz logic signal frequency v dd2 supply current i dd2 (q) 5 v/3 v operation 0.9 1.5 ma dc to 1 mhz logic signal frequency 3 v/5 v operation 1.5 2.1 ma dc to 1 mhz logic signal frequency 10 mbps (brwz and crwz grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 5.6 7.0 ma 5 mhz logic signal frequency 3 v/5 v operation 3.0 4.2 ma 5 mhz logic signal frequency v dd2 supply current i dd2 (10) 5 v/3 v operation 3.0 4.2 ma 5 mhz logic signal frequency 3 v/5 v operation 5.6 7.0 ma 5 mhz logic signal frequency 90 mbps (crwz grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 44 62 ma 45 mhz logic signal frequency 3 v/5 v operation 24 39 ma 45 mhz logic signal frequency v dd2 supply current i dd2 (90) 5 v/3 v operation 24 39 ma 45 mhz logic signal frequency 3 v/5 v operation 44 62 ma 45 mhz logic signal frequency for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 5 v/3 v operation 2.0 v 3 v/5 v operation 1.6 v logic low input threshold v il , v el 5 v/3 v operation 0.8 v 3 v/5 v operation 0.4 v logic high output voltages v oah , v obh , v och , v odh (v dd1 or v dd2 ) ? 0.1 (v dd1 or v dd2 ) v i ox = ?20 a, v ix = v ixh (v dd1 or v dd2 ) ? 0.4 (v dd1 or v dd2 ) ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal, v obl , v ocl , v odl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum240xarwz minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 50 70 100 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/ t pskod 50 ns c l = 15 pf, cmos signal levels adum240xbrwz minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 15 35 50 ns c l = 15 pf, cmos signal levels
data sheet adum2400/adum2401/adum2402 rev. d | page 9 of 24 parameter symbol min typ max unit test conditions pulse width distortion, |t plh ? t phl | 5 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 22 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 6 ns c l = 15 pf, cmos signal levels adum240xcrwz minimum pulse width 3 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 4 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 30 40 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 5 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 14 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 2 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f c l = 15 pf, cmos signal levels 5 v/3 v operation 3.0 ns 3 v/5 v operation 2.5 ns common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 5 v/3 v operation 1.2 mbps 3 v/5 v operation 1.1 mbps input dynamic supply current per channel 9 i ddi (d) 5 v/3 v operation 0.19 ma/mbps 3 v/5 v operation 0.10 ma/mbps output dynamic supply current per channel 9 i ddo (d) 5 v/3 v operation 0.03 ma/mbps 3 v/5 v operation 0.05 ma/mbps 1 all voltages are relative to their respective ground. 2 supply current values are for all four ch annels combined running at identical data rates. output supply current values are spe cified with no output load present. the supply current associated with an individual ch annel operating at a given data rate can be calculated as de scribed in the power consumption section. see figure 8 through figure 10 for information on per ch annel supply current as a function of data rate for unloaded an d loaded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for adum2400/adum2401/ adum2402 channel configurations. 3 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposing di rectional channel-to-channel match ing is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 8 through figure 10 for information on per channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating per channel supply current for a given data rate.
adum2400/adum2401/adum2402 data sheet rev. d | page 10 of 24 package characteristics table 4. parameter symbol min typ max unit test conditions resistance (input to output) 1 r i-o 10 12 capacitance (input to output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-case thermal resistance, side 1 jci 33 c/w thermocouple located at center of package underside ic junction-to-case thermal resistance, side 2 jco 28 c/w 1 device considered a two-terminal device: pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, and pin 8 shorted together and pin 9 , pin 10, pin 11, pin 12, pin 13, pin 14, pin 15, and pin 16 shorted together. 2 input capacitance is from any input data pin to ground. regulatory information the adum240x are approved by the organizations listed in table 5. refer to table 10 and the insulation lifetime section for det ails regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. table 5. ul csa vde recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884-10): 2006-12 2 single protection 5000 v rms isolation voltage basic insulation per csa 60950-1-07 and iec 60950-1, 600 v rms (848 v peak) maximum working voltage reinforced insulation, 846 v peak rw-16 package: reinforced insulation per csa 60950-1-07 and iec 60950-1, 380 v rms (537 v peak) maximum working voltage; reinforced insulation per iec 60601-1 125 v rms (176 v peak) maximum working voltage ri-16 package: reinforced insulation per csa 60950-1-07 and iec 60950-1, 400 v rms (565 v peak) maximum working voltage; reinforced insulation per iec 60601-1 250 v rms (353 v peak) maximum working voltage file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul1577, each adum240x is proof tested by a pplying an insulation test voltage 6000 v rms for 1 second (cur rent leakage detectio n limit = 10 a). 2 in accordance with din v vde v 0884-10, each adum240x is pr oof tested by applying an insulati on test voltage 1590 v peak for 1 sec (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 0884-10 approval. insulation and safety-related specifications table 6. parameter symbol value unit conditions rated dielectric insulation voltage 5000 v rms 1-minute duration minimum external air gap l(i01) 8.0 min mm distance measured from input terminals to output terminals, shortest distance through air along the pcb mounting plane, as an aid to pc board layout minimum external tracking (creepage) rw-16 package l(i02) 7.7 min mm measured from input termin als to output terminals, shortest distance path along body minimum external tracking (creepage) ri-16 package l(i02) 8.3 min mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
data sheet adum2400/adum2401/adum2402 rev. d | page 11 of 24 din v vde v 0884-10 (vde v 0884-10) insulation characteristics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety d ata is ensured by means of protective circuits. note that the * marking on packages denotes din v vde v 0884-10 approval for 846 v peak working voltage. table 7. description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 300 v rms i to iv for rated mains voltage 450 v rms i to ii for rated mains voltage 600 v rms i to ii climatic classification 40/105/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 846 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1590 v peak input-to-output test voltage, method a v pr after environmental tests subgroup 1 v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc 1375 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 1018 v peak highest allowable overvoltage transient overvoltage, t tr = 10 seconds v tr 6000 v peak safety-limiting values maximum value allowed in the event of a failure; see figure 4 case temperature t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s v io = 500 v r s >10 9 case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side #1 side #2 05007-004 figure 4. thermal derating curve, dependence of safety limiting values with case temperature per din v vde v 0884-10 recommended operat ing conditions table 8. parameter rating operating temperature (t a ) ?40c to +105c supply voltages 1 (v dd1 , v dd2 ) 2.7 v to 5.5 v input signal rise and fall times 1.0 ms 1 all voltages are relative to their respective ground.
adum2400/adum2401/adum2402 data sheet rev. d | page 12 of 24 absolute maximum ratings table 9. parameter rating storage temperature range (t st ) ?65c to +150c ambient operating temperature range (t a ) ?40c to +105c supply voltage range (v dd1 , v dd2 ) 1 ?0.5 v to +7.0 v input voltage range (v ia , v ib , v ic , v id , v e1 , v e2 ) 1, 2 ?0.5 v to v ddi + 0.5 v output voltage range (v oa , v ob , v oc , v od ) 1, 2 ?0.5 v to v ddo + 0.5 v average output current per pin 3 side 1 (i o1 ) ?18 ma to +18 ma side 2 (i o2 ) ?22 ma to +22 ma common-mode transients 4 ?100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pc board layout section. 3 see figure 4 for maximum rated curre nt values for various temperatures. 4 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the abso lute maximum rating can cause latch- up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 10. maximum continuous working voltage 1 parameter max unit constraint ac voltage, bipolar waveform 565 v peak 50-year minimum lifetime ac voltage, unipolar waveform reinforced insulation 846 v peak maximum approved working voltage per iec 60950-1 and vde v 0884-10 dc voltage reinforced insulation 846 v peak maximum approved working voltage per iec 60950-1 and vde v 0884-10 1 refers to continuous voltage magnitude imposed across the isol ation barrier. see the insulation lifetime section for more deta ils. table 11. truth table (positive logic) v ix input 1 v ex input v ddi state 1 v ddo state 1 v ox output 1 notes h h or nc powered powered h l h or nc powered powered l x l powered powered z x h or nc unpowered powered h outputs re turn to input state within 1 s of v ddi power restoration. x l unpowered powered z x x powered unpowered indeterminate outputs return to input state within 1 s of v ddo power restoration if v ex state is h or nc. outputs return to high impedance state within 8 ns of v ddo power restoration if v ex state is l. 1 v ix and v ox refer to the input and output signals of a given channel (a, b, c, or d). v ex refers to the output enable signal on the same side as the v ox outputs. v ddi and v ddo refer to the supply voltages on the input and output sides of the given channel, respectively.
data sheet adum2400/adum2401/adum2402 rev. d | page 13 of 24 pin configurations and function descriptions 05007-005 v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v id 6 v od 11 nc 7 v e2 10 *gnd 1 8 gnd 2 * 9 nc = no connect adum2400 top view (not to scale) *pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. figure 5. adum2400 pin configuration table 12. adum2400 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v id logic input d. 7 nc no connect. 8 gnd 1 ground 1. ground reference for isolator side 1. 9 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa , v ob , v oc , and v od outputs are enabled when v e2 is high or disconnected. v oa , v ob , v oc , and v od outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 11 v od logic output d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
adum2400/adum2401/adum2402 data sheet rev. d | page 14 of 24 05007-006 v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 11 v e1 7 v e2 10 *gnd 1 8 gnd 2 * 9 adum2401 top view (not to scale) *pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. figure 6. adum2401 pin configuration table 13. adum2401 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 v e1 output enable 1. active high logic input. v od output is enabled when v e1 is high or disconnected. v od is disabled when v e1 is low. in noisy environments, connecting v e1 to an external logic high or low is recommended. 8 gnd 1 ground 1. ground reference for isolator side 1. 9 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa , v ob , and v oc outputs are enabled when v e2 is high or disconnected. v oa , v ob , and v oc outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 11 v id logic input d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
data sheet adum2400/adum2401/adum2402 rev. d | page 15 of 24 05007-007 v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v oc 5 v ic 12 v od 6 v id 11 v e1 7 v e2 10 *gnd 1 8 gnd 2 * 9 adum2402 top view (not to scale) * pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. figure 7. adum2402 pin configuration table 14. adum2402 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 v e1 output enable 1. active high logic input. v oc and v od outputs are enabled when v e1 is high or disconnected. v oc and v od outputs are disabled when v e1 is low. in noisy environments, connecting v e1 to an external logic high or low is recommended. 8 gnd 1 ground 1. ground reference for isolator side 1. 9 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa and v ob outputs are enabled when v e2 is high or disconnected. v oa and v ob outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
adum2400/adum2401/adum2402 data sheet rev. d | page 16 of 24 typical performance characteristics 05007-008 data rate (mbps) current/channel (ma) 0 0 10 5 15 20 20 60 80 40 100 5v 3v figure 8. typical input supply current per channel vs. data rate for 5 v and 3 v operation (no output load) 05007-009 data rate (mbps) current/channel (ma) 0 0 3 2 1 4 5 6 20 60 80 40 100 5v 3v figure 9. typical output supply current per channel vs. data rate for 5 v and 3 v operation (no output load) 05007-010 data rate (mbps) current/channel (ma) 0 0 6 4 2 8 10 20 60 80 40 100 5v 3v figure 10. typical output su pply current per channel vs. data rate for 5 v and 3 v operation (15 pf output load) 05007-011 data rate (mbps) current (ma) 0 0 40 50 20 10 30 60 70 80 20 60 80 40 100 5v 3v figure 11. typical adum2400 v dd1 supply current vs. data rate for 5 v and 3 v operation 05007-012 data rate (mbps) current (ma) 0 0 10 10 5 15 20 20 60 80 40 100 5v 3v figure 12. typical adum2400 v dd2 supply current vs. data rate for 5 v and 3 v operation 05007-013 data rate (mbps) current (ma) 0 0 25 20 15 10 5 30 35 20 60 80 40 100 5v 3v figure 13. typical adum2401 v dd1 supply current vs. data rate for 5 v and 3 v operation
data sheet adum2400/adum2401/adum2402 rev. d | page 17 of 24 05007-014 data rate (mbps) current (ma) 0 0 20 15 10 5 30 25 35 40 20 60 80 40 100 5v 3v figure 14. typical adum2401 v dd2 supply current vs. data rate for 5 v and 3 v operation 05007-015 data rate (mbps) current (ma) 0 0 25 20 15 10 5 45 40 35 30 50 20 60 80 40 100 5v 3v figure 15. typical adum2402 v dd1 or v dd2 supply current vs. data rate for 5 v and 3 v operation temperature (c) propagation delay (ns) ?50 ?25 25 30 35 40 05075 25 100 05007-016 3v 5v figure 16. propagation delay vs. temperature, c grade
adum2400/adum2401/adum2402 data sheet rev. d | page 18 of 24 application information pc board layout the adum240x digital isolator requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins (see figure 17). bypass capacitors are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v dd2 . the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. bypassing between pin 1 and pin 8 and between pin 9 and pin 16 should be considered unless the ground pair on each package side are connected close to the package. v dd1 gnd 1 v ia v ib v ic/ v oc v id/ v od v e1 gnd 1 v dd2 gnd 2 v oa v ob v oc/ v ic v od/ v id v e2 gnd 2 05007-017 figure 17. recommended printed circuit board layout in applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this could cause voltage differentials between pins exceeding the devices absolute maximum ratings, thereby leading to latch-up or permanent damage. propagation delay-related parameters propagation delay is a parameter that describes the length of time it takes for a logic signal to propagate through a component. the propagation delay to a logic low output can differ from the propagation delay to logic high. input ( v ix ) output (v ox ) t plh t phl 50% 50% 05007-018 figure 18. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signals timing is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs among channels within a single adum240x component. propagation delay skew refers to the maximum amount the propagation delay differs among multiple adum240x components operated under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. the decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than ~1 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses for more than approximately 5 s, the input side is assumed to be without power or nonfunctional; in which case, the isolator output is forced to a default state (see table 11) by the watchdog timer circuit. the limitation on the adum240xs magnetic field immunity is set by the condition in which induced voltage in the transformers receiving coil is large enough to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3 v operating condition of the adum240x is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, therefore establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = (? d / dt )?r n 2 ; n = 1, 2,, n where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum240x and an imposed requirement that the induced voltage be at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 19. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 05007-019 figure 19. maximum allowable external magnetic flux density
data sheet adum2400/adum2401/adum2402 rev. d | page 19 of 24 for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 v to 0.75 vstill well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum240x transformers. figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. as can be seen, the adum240x is immune and can be affected only by extremely large currents operated at high frequency and very close to the component. for the 1 mhz example noted, place a 0.5 ka current 5 mm away from the adum240x to affect the components operation. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 05007-020 figure 20. maximum allowable current for various current-to-adum240x spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the supply current at a given channel of the adum240x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. for each input channel, the supply current is given by: i ddi = i ddi (q) f 0.5 f r i ddi = i ddi (d) (2 f ? f r ) + i ddi (q) f > 0.5 f r for each output channel, the supply current is given by: i ddo = i ddo (q) f 0.5 f r i ddo = ( i ddo (d) + (0.5 10 -3 c l v ddo ) (2 f ? f r ) + i ddo (q) f > 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (mhz, half of the input data rate, nrz signaling). f r is the input stage refresh rate (mbps). i ddi (q) , i ddo (q) are the specified input and output quiescent supply currents (ma). to calculate the total i dd1 and i dd2 , the supply currents for each input and output channel corresponding to i dd1 and i dd2 are calculated and totaled. figure 8 and figure 9 provide per channel supply currents as a function of data rate for an unloaded output condition. figure 10 provides per channel supply current as a function of data rate for a 15 pf output condition. figure 11 through figure 15 provide the total i dd1 and i dd2 as a function of data rate for the adum2400/adum2401/ adum2402 channel configurations.
adum2400/adum2401/adum2402 data sheet rev. d | page 20 of 24 insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the adum240x. analog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum csa/vde approved working voltages. in many cases, the approved working voltage is higher than the 50-year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the adum240x depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 21, figure 22, and figure 23 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. the goal of a 50-year operating lifetime under the ac bipolar condition determines analog devices recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50-year service life. the working voltages listed in table 10 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. any cross-insulation voltage waveform that does not conform to figure 22 or figure 23 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50-year lifetime voltage value listed in table 10. note that the voltage presented in figure 22 is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 05007-021 figure 21. bipolar ac waveform 0v rated peak voltage 05007-022 figure 22. unipolar ac waveform 0v rated peak voltage 05007-023 figure 23. dc waveform
data sheet adum2400/adum2401/adum2402 rev. d | page 21 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 24. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-ac 10-12-2010-a 13.00 (0.5118) 12.60 (0.4961) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) 8 0 16 9 8 1 1.27 (0.0500) bsc seating plane figure 25.16-lead standard small outline package, with increased creepage [soic_ic] wide body (ri-16-1) dimension shown in millimeters and (inches)
adum2400/adum2401/adum2402 data sheet rev. d | page 22 of 24 ordering guide model 1 , 2 number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range package description package option adum2400arwz 4 0 1 100 40 ?40c to +105c 16-lead soic_w rw-16 adum2400brwz 4 0 10 50 3 ?40c to +105c 16-lead soic_w rw-16 adum2400crwz 4 0 90 32 2 ?40c to +105c 16-lead soic_w rw-16 ADUM2400ARIZ 4 0 1 100 40 ?40c to +105c 16-lead soic_ic ri-16-1 adum2400briz 4 0 10 50 3 ?40c to +105c 16-lead soic_ic ri-16-1 adum2400criz 4 0 90 32 2 ?40c to +105c 16-lead soic_ic ri-16-1 adum2401arwz 3 1 1 100 40 ?40c to +105c 16-lead soic_w rw-16 adum2401brwz 3 1 10 50 3 ?40c to +105c 16-lead soic_w rw-16 adum2401crwz 3 1 90 32 2 ?40c to +105c 16-lead soic_w rw-16 adum2401ariz 3 1 1 100 40 ?40c to +105c 16-lead soic_ic ri-16-1 adum2401briz 3 1 10 50 3 ?40c to +105c 16-lead soic_ic ri-16-1 adum2401criz 3 1 90 32 2 ?40c to +105c 16-lead soic_ic ri-16-1 adum2402arwz 2 2 1 100 40 ?40c to +105c 16-lead soic_w rw-16 adum2402brwz 2 2 10 50 3 ?40c to +105c 16-lead soic_w rw-16 adum2402crwz 2 2 90 32 2 ?40c to +105c 16-lead soic_w rw-16 adum2402ariz 2 2 1 100 40 ?40c to +105c 16-lead soic_ic ri-16-1 adum2402briz 2 2 10 50 3 ?40c to +105c 16-lead soic_ic ri-16-1 adum2402criz 2 2 90 32 2 ?40c to +105c 16-lead soic_ic ri-16-1 1 tape and reel is available. the addi tion of an -rl suffix de signates a 13 (1,000 unit s) tape and reel option. 2 z = rohs compliant part.
data sheet adum2400/adum2401/adum2402 rev. d | page 23 of 24 notes
adum2400/adum2401/adum2402 data sheet rev. d | page 24 of 24 notes ?2005C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05007-0-8/11(d)

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